In a computer or other electronic system, clock signals may be used to control and sequence the flow of data between sequential storage elements, such as registers or latches on an integrated circuit (IC). A clock circuit including a phase-locked loop may be useful to maintain precise phase relationships between a reference clock signal and a distributed clock signal that is used to sequence digital logic or other circuit elements. Precise clock phase relationships may be useful in achieving known and efficient timing relationships between sequential logic elements.
A phase-locked loop circuit may detect phase differences between a reference clock signal and a distributed clock signal, and generate control signals based on those phase differences. The control signals may be used to adjust the timing and/or frequency of a clock generation circuit such as a voltage-controlled oscillator (VCO), or a delay-locked loop (DLL), the output of which may be distributed to a plurality of logic or other circuit elements.